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Design Services |
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1. |
FPGA Design (Job Code: CGC/FD)
Location: Bangalore
Positions: Project Managers, Project Leads, Technical Leads,
Sr. Design Engineers and Design Engineers
Qualification: M.E/M.Tech, B.E / B.Tech or equivalent in Electronics / Communication, Computer Science.
Experience: 2 to 10 years
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Multimedia (MPEG, Windows Media, DVB) |
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Telecom (SONET, ATM) |
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Networking (Ethernet, TCP/IP) |
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Storage Technologies ( iSCSI / SATA / Fiber Channel) |
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Processors (MIPS, ARM, PPC) |
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Interfaces (USB, PCIe, PCI-X) & Memories (DDR/DDR2, RLDRAM) |
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| Required Expertise: |
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Expertise in VHDL/Verilog RTL Coding, SystemC/ System Verilog |
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Expertise in FPGA Synthesis and PAR tools. |
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Experience in system level architecture development would be preferred. |
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| Skillsets: |
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FPGA |
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Verilog |
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VHDL |
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RTL |
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Synthesis |
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Multimedia |
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Networking |
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Telecom |
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Storage |
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Interfaces |
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 Click to E-mail your resume |
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2a. |
Verification (Job Code:CGC/VR)
Location: Bangalore
Positions: Project Managers
Qualification: M.E/M.Tech, B.E / B.Tech or equivalent in Electronics / Communication, Computer Science.
Experience: 2 to 10 years
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| Domains: |
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Multimedia (MPEG, Windows Media, DVB) |
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Networking (Ethernet, TCP/IP) |
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Processors (MIPS, ARM, PPC) |
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Interfaces (USB, PCIe, PCI-X) & Memories (DDR/DDR2, RLDRAM) |
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| Required expertise: |
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Verification languages System C/System Verilog/Vera/Specman |
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Test plan definition, coverage driven verification |
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Test bench development & functional modeling |
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Should have managed at least 3 or 4 large verification projects |
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| Skillsets: |
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VHDL/ Verilog / System Verilog based Test bench development. |
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Processor / Bus functional modeling experience. |
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Knowledge of System C |
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Scripting knowledge in either PERL, TCL/TK, AWK, SED, Shell Programming |
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3. |
Hardware Design (Job Code:CGC/HD) |
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Location: Bangalore
Positions:Project Managers, Project Leads, Technical Leads,
Sr. Design Engineers, Design Engineers
Qualification: M.E/M.Tech, B.E / B.Tech or equivalent in Electronics / Communication, Computer Science.
Experience: Relevant experience of 2-10 years
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| Domains: |
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Multimedia (MPEG, Windows Media, DVB) |
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Telecom (SONET, ATM) |
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Networking (Ethernet, TCP/IP) |
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Storage Technologies ( iSCSI / SATA / Fiber Channel) |
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Processors (MIPS, ARM, PPC) |
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Interfaces (USB, PCIe, PCI-X) & Memories (DDR/DDR2, RLDRAM) |
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| Required expertise: |
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Logic design and debugging expertise |
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Hardware-software interfacing |
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Sound understanding of high-speed board design and Signal Integrity concepts. |
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| Skillsets: |
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Hardware |
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Board |
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Logic |
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Embedded System Design |
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Multimedia |
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Telecom |
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Storage |
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Interfaces |
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Click to E-mail your resume |
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4a. |
ASIC Design (Job Code: CGC/AD)
Location: Bangalore
Positions: Project Leads, Technical Leads, Sr. Design Engineers,
Sr. Software Engineers and Design Engineers
Qualification: M.E/M.Tech, B.E / B.Tech or equivalent in Electronics / Communication, Computer Science.
Experience: 2 to 10 years
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| Domains: |
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Multimedia (MPEG, Windows Media, DVB) |
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Telecom (SONET, ATM) |
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Networking (Ethernet, TCP/IP) |
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Storage Technologies ( iSCSI / SATA / Fiber Channel) |
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Processors (MIPS, ARM, PPC) |
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Interfaces (USB, PCIe, PCI-X) & Memories (DDR/DDR2, RLDRAM) |
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| Required expertise: |
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SOC Architecture, Micro- architecture, RTL Design for ASICs. |
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ASIC Synthesis, STA, DFT, P&R, DRC, IC Layout Design, Physical Verification & Formal Verification |
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| Skillsets: |
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Multimedia |
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Networking |
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Telecom |
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Storage |
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Interfaces |
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Processor |
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ASIC |
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Front end |
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VHDL |
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Verilog |
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RTL Architecture |
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Micro Architecture |
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Backend |
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Synthesis |
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STA |
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DRC |
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LVS |
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DFT |
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ATPG |
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Formal |
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Timing closure |
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Click to E-mail your resume |
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4b. |
ASIC Front end Design (Job Code: CGC/AD) |
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Location: Bangalore
Positions: Project Manager
Qualification: M.E/M.Tech, B.E / B.Tech or equivalent in Electronics / Communication, Computer Science.
Experience: Experience: 10-12 years |
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| Domains: |
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Networking (Ethernet, TCP/IP)
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Processors (MIPS, ARM, PPC) |
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Interfaces (USB, PCIe, PCI-X) & Memories (DDR/DDR2, RLDRAM) |
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| Required expertise: |
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Micro- architecture, RTL Design for ASICs.
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Verification at module level |
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Should have at least executed at least 3 ASIC front end projects |
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| Skillsets: |
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VHDL / Verilog
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Micro Architecture definition |
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Scripting using Perl / tcl |
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Top level RTL integration |
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Click to E-mail your resume |
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5. |
Embedded Software (Job Code:CGC/ES)
Location: Bangalore
Positions: Project Managers, Project Leads, Technical Leads,
Sr. Design Engineers and Design Engineers.
Qualification: M.E/M.Tech, B.E / B.Tech or equivalent in Electronics / Communication, Computer Science.
Experience: 2 to 10 years
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| Domains: |
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Multimedia (MPEG, Windows Media, DVB) |
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Telecom (SONET, ATM) |
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Networking (Ethernet, TCP/IP) |
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Storage Technologies ( iSCSI / SATA / Fiber Channel) |
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Processors (MIPS, ARM, PPC) |
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Interfaces (USB, PCIe, PCI-X) & Memories (DDR/DDR2, RLDRAM) |
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| Required Expertise: |
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Multimedia |
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Networking |
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Telecom |
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Storage |
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Interfaces |
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Embedded |
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TCP/IP |
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Linux |
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VxWorks |
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Device drivers |
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C |
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C++ |
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Firmware |
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Software |
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| Skillsets: |
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Embedded OS |
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Thorough knowledge of RTOS concepts and experience in VxWorks / Embedded Linux/ WinCE |
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Device Drivers and APIs |
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Experience in Device Driver and API development for VxWorks, Linux, windows, Win CE, QNX
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Protocol Stacks |
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Click to E-mail your resume |
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