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Bangalore
December 11, 2007 |
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Taj Residency,
41/3,
Mahatma Gandhi Road
Bangalore 560 001
Karnataka, India
Tel : (91-80) 6660 4444 |
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Hyderabad
December 13, 2007 |
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The ITC Kakatiya Sheraton Hotel & Towers,
63-3-1187, Begumpet
Hyderabad 500016, India
Tel : (91-40) 23400132 |
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| From |
Duration |
Title |
| 8:00 - 9:00 |
1:00 |
Registration and Visit to Ecosystem Partners Booth |
| 9:00 - 9:05 |
0:05 |
Welcome and Introduction |
| 9:05 - 9:10 |
0:05 |
First Lucky Draw |
| 9:10 -10:00 |
0:50 |
Digital Convergence is Finally Here: How can Xilinx help?
Speaker: Krishna Rangasayee - Sr. Director, Vertical Marketing & Partnerships, Xilinx, San Jose |
| 10:00 - 10:50 |
0:50 |
Building A Globally Successful Technology Product Company From India
Speaker: Sanjay Nayak - CEO and Managing Director, Tejas Networks, Bangalore |
| 10:50 - 11:10 |
0:20 |
Tea Break |
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Track A |
Track B |
Track C |
| 11:10 - 12:10 |
0:60 |
Xilinx Solutions for Wired & Wireless Communications Markets
Speaker: Amit Dhir - Director - Infrastructure Vertical Markets, Xilinx, San Jose |
Xilinx Solutions for Industrial, Scientific & Medical Markets Speaker:
Niladri Roy - Sr.Manager, ISM Vertical Markets, Xilinx, San Jose |
Xilinx Aerospace & Defense overview
Speaker:
Joel Le Mauff, Aerospace & Defense Sales Development Manager, Xilinx, France |
| 12:10 - 13:10 |
0:60 |
Reduce Serial I/O Power, Cost and Complexity with Virtex™-5 LXT FPGAs
Speaker:
Wicky Pillai - Principal Consultant, CG-CoreEl, Bangalore |
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DSP Design Automation using Xilinx FPGAs
| The keynote speaker will share with the audience Xilinx’s view of the opportunity and challenges represented by Digital Convergence – both on the Infrastructure and the Consumer front. The speaker will also present Xilinx’s view on our value proposition and solutions by various end markets, key trends, and the role Xilinx intends to play in helping customers capitalize on the business opportunity at hand while managing the challenges. |
| Tejas Networks is a pioneering product company in India, developing next-generation optical networking products for the global markets, leveraging the strengths of it's R&D team in India to gain competitive edge. Sanjay Nayak, CEO and Managing Director of Tejas Networks will share his thoughts on what it takes to build a globally successful technology products company from India. India, witnessing the fiercest of competition in the communications industry, allows Tejas Networks to build products that are cutting edge while still being competitive to be able to win in the Indian market and hence in any other region of the world. While R&D is the core strength, it is important to evolve new business models to be able to compete globally. Programmable Logic products have been inherently used to provide the competitive edge to Tejas products, and Mr.Nayak will also share how the partnership with Xilinx helped contribute to Tejas' overall success.
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| An overview of Xilinx solutions for wired and wireless communications in enterprise and telecom (metro/access/transport), including wired communications solutions in the line card, switch card and processor card, and wireless communications solutions in the radio card, channel card and network card. |
| An overview of Xilinx high performance solutions for ISM vertical applications including industrial networking, machine vision, surveillance and motor control, followed by a brief look at the company’s solutions roadmap. |
| This presentation will summarize Xilinx solutions for aerospace and defense applications. Discussion will review the QPRO™ family roadmap, specific packaging, and solutions for military/defense, avionics and aeropace applications. |
| A discussion on how to simplify design using a low-power, area-efficient, serial I/O FPGA solution. |
| An overview on how Xilinx software design tools can help improve designer productivity in today’s increasingly complex, FPGA-based designs. |
| This session will highlight the advantage of using Xilinx silicon and software solutions to reduce DSP development cycle time, specifically for defense-related applications. |
| Learn how to implement a PCI Express application, taking full advantage of the programmable features in an FPGA for backplane, cabled and other types of designs. |
| Overview on how to leverage the unique DeviceDNA design security features of the low-cost Spartan-3 Generation FPGA family to protect products and profits from the increased prevalence of counterfeiting in the semiconductor electronics industry. |
| National Aerospace Laboratories customised, indigenously developed ‘FLOSOLVER V’ parallel computer uses high speed serial I/O transceivers of Xilinx Virtex II Pro family for data communication at 1 Gb/s.The latest version ‘FLOSOLVER VII’, under development, uses 16 Channel serial I/O GTP’s in Virtex 5 LX 110T, aiming communication speed above 3 Gb/s. |
| In today's FPGA devices, the dominant component of a typical path delay is interconnect. For example, in 130 nm Xilinx Virtex-II Pro designs, interconnect accounts for close to 50% of the total path delay. For newer FPGA families, such as Xilinx Virtex-4, interconnect can account for around 80%. Traditional physical synthesis tools work on a post place-and-route netlist with back-annotated physical delay information. However, the moment the optimization engine starts to change the netlist, the accuracy of the timing and placement information begins to deteriorate. Precision RTL's physically aware synthesis performs its physical optimization with a delay accuracy close to that of physical synthesis by using the timing information derived from its internal generic placer and static timing analyzer. This capability eliminates the prerequisite of performing a full place-and-route on the netlist as required by traditional physical synthesis tools, saving significant runtime, and able to achieve better Quality of Results. |
| This presentation highlights and demonstrates two unique capabilities that empower Agilent Logic Analyzers
1. Automated Dynamic Probing for Xilnx FPGAs helps you to quickly access upto 128 internal FPGA signals per debug pin. Automated import of signal names from FPGA design tools & Auto-pin mapping eliminates mistakes and saves time.
2. Demodulation capabilities of Vector Signal Analysis (VSA) software running on logic analyzer performs signal analysis functions such as I/Q analysis, EVM, Fourier spectrum, etc. on the digital signal captured by the Logic Analyzer.
Received |
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See Wind River commitment towards Aerospace and Defense industry with various certifications and VxWorks 653 feature benefits. In the presentation, we will also describes our ARINC 653 implementation for a technical audience and describes the advantages of our new VxWorks 653 Platform 2.2.
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| A tutorial on how to address various memory interface design challenges ranging from low-cost implementations to high-bandwidth and short-latency memory controllers – including tips and tricks for using Xilinx software and hardware verification tools to shorten the design cycle. |
| A discussion of how to use MicroBlaze processors with Xilinx EDK 9.2i tools to design high performance systems. Real-world customer designs can now include MicroBlaze processors with memory management unit to enable use of the Linux operating system. EDK 9.2i tools support MPMC3, TEMAC and PCIe hard and soft blocks, and USB. |
| An overview of military communications and software defined radio solutions, including silicon, tools, IP and development platforms. |
| The keynote speaker will share with the audience Xilinx’s view of the opportunity and challenges represented by Digital Convergence – both on the Infrastructure and the Consumer front. The speaker will also present Xilinx’s view on our value proposition and solutions by various end markets, key trends, and the role Xilinx intends to play in helping customers capitalize on the business opportunity at hand while managing the challenges. |
| An overview of Xilinx high performance solutions for ISM vertical applications including industrial networking, machine vision, surveillance and motor control, followed by a brief look at the company’s solutions roadmap. |
| This presentation will summarize Xilinx solutions for aerospace and defense applications. Discussion will review the QPRO™ family roadmap, specific packaging, and solutions for military/defense, avionics and aeropace applications. |
| An overview on how Xilinx software design tools can help improve designer productivity in today’s increasingly complex, FPGA-based designs. |
| This session will highlight the advantage of using Xilinx silicon and software solutions to reduce DSP development cycle time, specifically for defense-related applications. |
| Overview on how to leverage the unique DeviceDNA design security features of the low-cost Spartan-3 Generation FPGA family to protect products and profits from the increased prevalence of counterfeiting in the semiconductor electronics industry. |
| A tutorial on how to address various memory interface design challenges ranging from low-cost implementations to high-bandwidth and short-latency memory controllers – including tips and tricks for using Xilinx software and hardware verification tools to shorten the design cycle. |
| Learn how to implement a PCI Express application, taking full advantage of the programmable features in an FPGA for backplane, cabled and other types of designs. |
| Customer Success Story Hyderabad |
| In today's FPGA devices, the dominant component of a typical path delay is interconnect. For example, in 130 nm Xilinx Virtex-II Pro designs, interconnect accounts for close to 50% of the total path delay. For newer FPGA families, such as Xilinx Virtex-4, interconnect can account for around 80%. Traditional physical synthesis tools work on a post place-and-route netlist with back-annotated physical delay information. However, the moment the optimization engine starts to change the netlist, the accuracy of the timing and placement information begins to deteriorate. Precision RTL's physically aware synthesis performs its physical optimization with a delay accuracy close to that of physical synthesis by using the timing information derived from its internal generic placer and static timing analyzer. This capability eliminates the prerequisite of performing a full place-and-route on the netlist as required by traditional physical synthesis tools, saving significant runtime, and able to achieve better Quality of Results. |
| This presentation highlights and demonstrates two unique capabilities that empower Agilent Logic Analyzers
1. Automated Dynamic Probing for Xilnx FPGAs helps you to quickly access upto 128 internal FPGA signals per debug pin. Automated import of signal names from FPGA design tools & Auto-pin mapping eliminates mistakes and saves time.
2. Demodulation capabilities of Vector Signal Analysis (VSA) software running on logic analyzer performs signal analysis functions such as I/Q analysis, EVM, Fourier spectrum, etc. on the digital signal captured by the Logic Analyzer.
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| A discussion of how to use Microblaze processor and Xilinx EDK 9.2i tools to design high performance systems. Real-world customer designs can now include Microblaze processor with MMU, running Linux, plus native support in EDK9.2i tools for MPMC3, TEMAC and PCIe hard and soft blocks, and USB. |
| An overview of military communications and software defined radio solutions, including silicon, tools, IP and development platforms. |
Speaker:
Hong Swee Lim, Sr. Product Marketing Manager, Embedded & DSP, Xilinx, Singapore |
| 13:10 - 14:00 |
0:50 |
Lunch |
| 14:00 - 14:10 |
0:10 |
Quiz and Prizes |
Quiz and Prizes |
Quiz and Prizes |
| 14:10 - 15:10 |
0:60 |
How to Design With and Take Advantage of the PCI Express® Compliant Endpoint Controller in Virtex-5 FPGAs
Speaker:
Krishna Kishore B - Design Engineer, Xilinx, Hyderabad |
Design Security Features of Xilinx Spartan-3 Generation FPGAs
Speaker:
Terence Lee, Sr.Marketing Manager, High Volume Products, Xilinx, Singapore |
NAL Customer Success Story - Using Xilinx's FPGA's for Customised Parallel Computing |
| 15:10 - 16:00 |
0:50 |
Mentor Graphics - Faster Timing closure for Xilinx FPGA's with physically aware synthesis technology - precision RTL plus
Speaker:
Mallikarjuna BS & Sachin Kakkat |
Agilent Technologies - Debug FPGA & Baseband designs through fully Automated FPGA Dynamic Probing and Unique Demodulation Capabilities of Agilent Logic Analyzers
Speaker:
Sanchit Bhatia |
Wind River - Wind River Commitment to Aerospace & Defense
Speaker:
Suneel Sinha |
| 16:00 - 16:20 |
0:20 |
Tea Break |
| 16:20 - 17:20 |
0:60 |
Low-Cost to High-Performance Memory Interface Design Made Easy with Xilinx Virtex and Spartan™ FPGAs
Speaker:
Karthi Palanisamy - Engineering Manager, Xilinx, Hyderabad |
Running Real-Time Linux on Xilinx Microblaze™ Embedded Processor
Speaker:
Rajesh Subramanian, Field Applications Manager, Avnet, Pune |
Xilinx solutions for Military Communications
Speaker:
Nihar Mastakar - Sr.Field Applications Engineer, NuHorizons, Bangalore |
| 17:20 - 17:40 |
0:20 |
Q/A, Wrap up, Second Lucky Draw |
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| Agenda[Hyderabad] |
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| From |
Duration |
Title |
| 8:00 - 9:00 |
1:00 |
Registration and Visit to Ecosystem Partners Booth |
| 9:00 - 9:05 |
0:05 |
Welcome and Introduction |
| 9:05 - 9:10 |
0:05 |
First Lucky Draw |
| 9:10 -10:00 |
0:50 |
Digital Convergence is Finally Here: How can Xilinx help? Speaker: Krishna Rangasayee - Sr. Director, Vertical Marketing & Partnerships, Xilinx, San Jose |
| 10:00 - 10:20 |
0:20 |
Tea Break |
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Track A |
Track B |
| 10:20 - 11:20 |
0:60 |
Xilinx Solutions for Industrial, Scientific & Medical Markets Speaker:
Niladri Roy - Sr.Manager, ISM Vertical Markets, Xilinx, San Jose |
Xilinx Aerospace & Defense overview Speaker:
Joel Le Mauff, Aerospace & Defense Sales Development Manager, Xilinx, France |
| 11:20 - 12:20 |
0:60 |
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| 12:20 - 13:20 |
0:60 |
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| 13:20 - 14:05 |
0:45 |
Lunch |
| 14:05- 14:10 |
0:05 |
Quiz and Prizes |
Quiz and Prizes |
| 14:10 - 15:10 |
0:60 |
How to Design With and Take Advantage of the PCI Express® Compliant Endpoint Controller in Virtex-5 FPGAs
Speaker:
Krishna Kishore B - Design Engineer, Xilinx, Hyderabad |
Customer success story |
| 15:10 - 16:00 |
0:50 |
Mentor Graphics - Faster Timing closure for Xilinx FPGA's with physically aware synthesis technology - precision RTL plus
Speaker:
Mallikarjuna BS & Sachin Kakkat |
Agilent Technologies - Debug FPGA & Baseband designs through fully Automated FPGA Dynamic Probing and Unique Demodulation Capabilities of Agilent Logic Analyzers
Speaker:
Sanchit Bhatia |
| 16:00 - 16:15 |
0:15 |
Tea Break |
| 16:15 - 17:15 |
0:60 |
Running Real-Time Linux on Xilinx Microblaze™ Embedded Processor
Speaker:
Rajesh Subramanian, Field Applications Manager, Avnet, Pune |
Xilinx solutions for Military Communications
Speaker:
Nihar Mastakar - Sr.Field Applications Engineer, NuHorizons, Bangalore |
| 17:15 - 17:30 |
0:15 |
Q/A, Wrap up, Second Lucky Draw |
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