We have development expertise in the area of ASIC process migration methodology for various Process technologies (For E.g 1 to 0.6 u, 0.6 to 0.35 u, 0.35 to 0.18 ,0.18 to 0.13u ). Our talented pool of engineers have the relevant skill sets in deliverables of Migration Project on Different ASIC Process Technology.

The conversion process in general involves the following:

	Design conversion from 0.6µ to 0.35 technology library
	Proving functional equivalence
	Timing Analysis Pre-layout Post-Layout
	Supporting the ASIC supplier’s layout and fabrication preparation

HDL Translated Netlist to Post Layout Verification life cycle deliverables are listed below:

	Understanding the Re-Spin Issues from a technology Prespective.
	Gate level Verification and Static Timing Analysis
	Functional ,timing and Formal Verification Methodology
	Improved Test Bench and Coverage Metrics For Corner case and Constrained Verification
	Module and Full chip Signoff STA to Improve Slack for the Newer micron Technology
	Multiple Clock Domain handling Capabilities
	Our infrastructure includes High end Servers to accommodate Regression Testing for the Simulations and generating reports
	State of the art Sign off EDA Suite of Tools Used

 

The key factor is the close association with the Library and Foundry to reduce the number of iteration in the project life cycle, handled in our process and milestones with the customer engagements.